l33786

People! The new amazing l33786 processor is here! More than ten powerful opcodes! Almost eight bits to the byte! Non-Uniform Memory Access for super-high performance!

We are also super-green! To conserve power, memory in our system is split in two halfs: low and high. Memory locations are physically 7-bit long, but this is not a limit for our CPU! Just store values below 127 in the low memory and values 128 or higher in high memory. There are 4 high memory locations and 4 low ones.

Two registers are provided, rl and rh. Low memory is wired to rl, high memory is wired to rh. Registers are not limited in the values they can store.

With unprecedented generosity, UCSB is giving you access to a version of l33786 that integrates an arithmetic coprocessor! The coprocessor can increment or decrement arbitrary memory locations. DMA! Amazing.

Here is our state-of-the-art RISC instruction set:

ldh {addr} will perform:rh = high_memory[addr]
ldh {addr} will perform:rl = low_memory[addr]
sth {addr} will perform:high_memory[addr] = rh
stl {addr} will perform:low_memory[addr] = rl
incl {addr} will perform:low_memory[addr]++
decl {addr} will perform:low_memory[addr]--
inch {addr} will perform:high_memory[addr]++
dech {addr} will perform:high_memory[addr]--
xor {dest} {src} will perform:dest = dest XOR src
shl rh {count} will perform:rh = rh << count
shr rl {count} will perform:rl = rl >> count

Addresses are integers in the range [0,3]. Example: "ldh 3".

I heard that if you load 146 in rl and 69 in rh something special may happen... What are you waiting for? Connect to port 3786 on 10.13.3.134 and start your limited trial of this amazing CPU!